The present invention relates to a method and an apparatus for decoding a digital signal, and, more particularly, to a digital signal recording/reproducing apparatus which performs a decoding process on recorded digital signals and a digital signal transmission apparatus which performs a decoding process on transmitted digital signals.
A digital signal recording/reproducing apparatus uses a PR (Partial Response) class IV algorithm that performs NRZI code conversion in order to improve the recording density of magnetic recording media and improve the S/N ratio of decoded digital signals. Because a magnetic recording/reproducing system has a differential characteristic, recording and reproduction of data spreads the signal waveform, which causes an intersymbol interference. The PR system uses the intersymbol interference positively to shape a signal such that the power spectrum of a code is adequate for the transmission characteristic of a transmission line.
FIG. 1 is a schematic block diagram of a conventional digital signal recording/reproducing apparatus 100 which uses the PR class IV algorithm. A precoder 1 has a modulo-2 digital adder 2a and a 1-bit delay operation element 3a and has the characteristic of 1/(1+D). The precoder 1 receives, for example, a digital input signal Din as shown in FIG. 1, and performs a process of 1/(1+D) on the input signal Din to convert the input signal Din to an NRZI code S1 as shown in FIG. 2. The polarity of the NRZI code is inverted every time the input signal Din rises from xe2x80x9c0xe2x80x9d to xe2x80x9c1xe2x80x9d. The polarity inversion means a transition of a signal value from xe2x80x9c1xe2x80x9d to xe2x80x9c0xe2x80x9d or from xe2x80x9c0xe2x80x9d to xe2x80x9c1xe2x80x9d.
A write buffer 4 whose structure is similar to that of the precoder 1 has the characteristic of 1/(1xe2x88x92D). The write buffer 4 produces an output signal S2 by giving an intersymbol interference opposite to the one that is given by a recording/reproducing system to the NRZI code S1 from the precoder 1.
A recording/reproducing system 5 has a write head 6, a recording medium 7 and a read head 8. The output signal S2 of the write buffer 4 is written on the recording medium 7 via the write head 6 and the written signal is read from the recording medium 7 via the read head 8.
The writing operation to the recording medium 7 by the write head 6 has the differential characteristic of (1xe2x88x92D), and the operation of the read head 8 and an equalizer 9 has the differential characteristic of (1+D). Therefore, the recording/reproducing system 5 and the equalizer 9 carry out a process of {(1xe2x88x92D)(1+D)}, thereby accomplishing PR class IV impulse response.
The equalizer 9 performs PR equalization on an analog read signal generated by the read head 8, thereby producing an equalization signal S3. The equalization signal S3 is a multi-value signal as shown in FIG. 2.
A comparator 10 compares the equalization signal S3 from the equalizer 9 with threshold values A and B (shown in FIG. 2) and produces a decoded signal Dout of xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d which coincides with the input signal Din. When the level of the equalization signal S3 is higher than the threshold value A or is lower than the threshold value B, xe2x80x9c1xe2x80x9d is output otherwise xe2x80x9c0xe2x80x9d is output.
For digital signal recording/reproducing apparatuses which use recording media, such as a floppy disk, that needs swapping, however, the format of signals to be recorded on recording media is specified. Since the specifications states that the input signal Din is recorded on the recording medium using only a write buffer, the digital signal recording/reproducing apparatuses cannot use a precoder.
A digital signal recording/reproducing apparatus of a peak detection type which does not use a precoder cannot implement PR-system based recording and reproduction operations using a precoder. As a solution to this shortcoming, Japanese Unexamined Patent Publication Nos. 5-325425, 5-307837, 8-147893 and 8-77712 disclose apparatuses capable of adapting the PR system without having a precoder at the preceding stage of the recording/reproducing system. However, decoding circuits in the apparatuses described in these publications are complicated.
By contrast, the recording/reproducing apparatus 100 in FIG. 1 is of a linear type, where the characteristics of the system do not change even if the order of the individual blocks is changed.
One possible modification is a recording/reproducing apparatus 110 shown in FIG. 3 which has a precoder equivalent circuit 11 located after the comparator 10. The write buffer 4, recording/reproducing system 5 and comparator 10 in FIG. 3 are identical to those in FIG. 1.
The operation of the recording/reproducing apparatus 110 in FIG. 3 will now be discussed referring to the waveform diagram of FIG. 4. The write buffer 4 receives the input signal Din and provides an output signal S4 according to the characteristic of (1xe2x88x92D) to the recording/reproducing system 5. The recording/reproducing system 5 provides its output signal having a characteristic of (1xe2x88x92D)(1+D) to the equalizer 9, which in turn provides an equalization signal S5 to the comparator 10. The comparator 10 performs a comparison operation and provides an output signal S6 to the precoder equivalent circuit 11. The precoder equivalent circuit 11 performs an operation of 1/(1+D) on the output signal S6, thus generating a decoded signal Dout which is substantially the same as the input signal Din.
Even if the input signal Din has been recorded on the recording medium 7 without using a precoder, the signal that is read by the recording/reproducing system 5 can be decoded by the PR system using the PR equalizer 9 and the precoder equivalent circuit 11.
If the operation of the recording/reproducing system 5 or the equalizer 9 in the digital signal recording/reproducing apparatus 110 causes an arbitrary bit b1 in the equalization signal S5 to contain noise n1 which is greater than the threshold value as shown in FIG. 5, however, the comparator 10 performs an operation different from the one illustrated in FIG. 4 so that the bit b1 of the output signal S6 is inverted. Then, the feedback loop of the precoder equivalent circuit 11 inverts all the bits in the decoded signal Dout after the bit b1, causing an error to propagate endlessly. This type of digital signal recording/reproducing apparatus is therefore not practical.
Accordingly, it is an object of the present invention to provide a digital signal decoding apparatus which performs a decoding operation using a PR system while suppressing propagation of an error without a precoder at the preceding stage of a recording/reproducing system or a transmission system.
In a first aspect of the present invention, a method of decoding a digital signal is provided. First, the digital signal is processed using a delay operation element in accordance with a frequency characteristic of 1+D, where D is an output signal of the delay operation element. The processed digital signal is converted to a conversion signal of at least three values having polarities of 0, positive and negative. A decoded signal is generated by processing the conversion signal in accordance with a frequency characteristic of 1/(1+D). Then, it is detected if there is a conversion error in the conversion signal and a correct signal is generated by restricting propagation of the conversion error to the decoded signal when the conversion error is detected.
In a second aspect of the present invention, a method of decoding a digital signal is provided. First, a 1/(1xe2x88x92D) process is performed on the digital signal using a delay operation element, where D is an output signal of the delay operation element to generate a write signal. The write signal is written on a recording medium in accordance with a (1xe2x88x92D) characteristic. The write signal written on the recording medium is read in accordance with a (1+D) characteristic and PR equalization is performed on the read signal to generate a PR equalization signal. Then, the PR equalization signal is converted to a 3-value signal of 1, 0 and xe2x88x921 and a decoded signal is generated by processing the 3-value signal in accordance with a frequency characteristic of 1/(1+D). A correct decoded signal is generated by restricting propagation of an error to the decoded signal when the output signal of the delay operation element is 1 or xe2x88x921 and the digital signal is 0, or when a polarity of the output signal of the delay operation element is opposite to a polarity of the digital signal.
In a third aspect of the present invention, a method of decoding a digital signal is provided. First, a 1/(1xe2x88x92D) process is performed on the digital signal using a delay operation element, where D is an output signal of the delay operation element to generate a transmission signal. The transmission signal is transmitted using a transmission line having a (1xe2x88x92D) characteristic and PR equalization is performed on the transmission signal in accordance with a (1+D) characteristic to generate a PR equalization signal. Then, the PR equalization signal is converted to a 3-value signal of 1, 0 and xe2x88x921 and a decoded signal is generated by processing the 3-value signal in accordance with a frequency characteristic of 1/(1+D). A correct decoded signal is generated by restricting propagation of an error to the decoded signal when the output signal of the delay operation element is 1 or xe2x88x921 and the digital signal is 0, or when a polarity of the output signal of the delay operation element is opposite to a polarity of the digital signal.
In a fourth aspect of the present invention, an apparatus for decoding a digital signal processed in accordance with a frequency characteristic of 1+D is provided. D is an output signal of a first delay operation element. The apparatus includes a comparator to convert the digital signal to a conversion signal of at least three values having polarities of 0, positive and negative. An error-propagation restriction circuit is connected to the comparator to generate a decoded signal by processing the conversion signal in accordance with a frequency characteristic of 1/(1+D). The error-propagation restriction circuit detects if there is a conversion error in the conversion signal, restricts propagation of the conversion error to the decoded signal when detecting the conversion error, and generates a correct decoded signal.
In a fifth aspect of the present invention, a digital signal recording/reproducing apparatus is provided. The apparatus includes a write buffer including a first delay operation element to perform a 1/(1xe2x88x92D) process on a digital signal, where D is an output signal of the first delay operation element, and generate a write signal. A recording/reproducing system is connected to the write buffer to write the write signal on a recording medium in accordance with a (1xe2x88x92D) characteristic and read the write signal written on the recording medium in accordance with a (1+D) characteristic. An equalizer is connected to the recording/reproducing system to perform PR equalization on the signal read by the recording/reproducing system and generate a PR equalization signal. A comparator is connected to the equalizer to convert the PR equalization signal to a 3-value signal of 1, 0 and xe2x88x921. An error-propagation restriction circuit is connected to the comparator and includes a second delay operation element to generate a decoded signal by processing the 3-value signal in accordance with a frequency characteristic of 1/(1+D). The error-propagation restriction circuit generates a correct decoded signal by restricting propagation of an error to the decoded signal when the output signal of the second delay operation element is positive or negative and the digital signal is 0, or when a polarity of the output signal of the second delay operation element is opposite to a polarity of the digital signal.
In a sixth aspect of the present invention, a digital signal transmission apparatus is provided. The apparatus includes a write buffer including a first delay operation element to perform a 1/(1xe2x88x92D) process on a digital signal, where D is an output signal of the first delay operation element, and generate a transmission signal. A transmission line is connected to the write buffer to transmit the transmission signal in accordance with a (1xe2x88x92D) characteristic. An equalizer is connected to the transmission line to perform PR equalization on the transmission signal, transmitted via the transmission line, in accordance with a (1+D) characteristic and generate a PR equalization signal. A comparator is connected to the equalize to convert the PR equalization signal to a 3-value signal of 1, 0 and xe2x88x921. An error-propagation restriction circuit is connected to the comparator and includes a second delay operation element to generate a decoded signal by processing the 3-value signal in accordance with a frequency characteristic of 1/(1+D). The error-propagation restriction circuit generates a correct decoded signal by restricting propagation of an error to the decoded signal when the output signal of the second delay operation element is positive or negative and the digital signal is 0, or when a polarity of the output signal of the second delay operation element is opposite to a polarity of the digital signal.
Other aspects and advantages of the invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.